1. Field of the Invention
This invention relates to a thin film crystal and a method for forming the same, particularly to a thin film crystal which is formed at a relatively lower temperature by controlling nucleation formation positions of a plurality of thin film crystal grains, and is controlled in the positions of the grain boundaries formed at the portion where adjoining crystal grains contact each other, and the sizes of the crystal grains, and can be applied to a thin film crystal to be utilized for, for example, electronic devices such as semiconductor devices, etc., optical devices, etc., and to a method for forming the same.
2. Related Background Art
As a method in the field of crystal formation technique which grow a crystalline thin film on a substrate such as amorphous substrate, etc., there has been proposed the method in which an amorphous thin film previously formed on a substrate is permitted to grow in solid phase by annealing at a low temperature not higher than the melting point. For example, there has been reported a method for forming a crystal that by annealing an amorphous Si thin film with a film thickness of about 100 nm formed on an amorphous SiO.sub.2 surface in an N.sub.2 atmosphere at 600.degree. C., the above amorphous Si thin film is crystallized to become a polycrystalline thin film with the maximum grain size of about 5 .mu.m [T. Noguchi, H. Hayashi and H. Oshima, 1987, Mat. Res. Soc. Symp. Proc., 106, Polysilicon and Interfaces 293 (Elaevier Science Publishing, New York, 1988)]. The surface of the polycrystalline thin film obtained according to this method remains flat, and therefore it can be used as such for formation of an electronic device such as MOS transistor or diode. Also, those devices obtained have relatively higher performances, because the average grain size of the polycrystal is by far greater as compared with conventional polycrystalline silicon, etc. deposited according to LPCVD method.
However, in this crystal formation method, although the crystal size is large, its distribution and the positions of the crystal grain boundaries are not controlled. For, in this case, since the crystallization of the amorphous material is based on solid phase epitaxial growth of the crystal nuclei generated randomly in the amorphous material by annealing, the position of the grain boundaries are also randomly formed, with the result that the grain sizes are distributed over a wide range. Therefore, the following problems arise by merely large average grain size of crystal grains. For example, in an MOS transistor, the size of the gate is similar to the crystal grain size, or lower than that, and therefore no grain boundary is included in the gate portion, or several grain boundaries are included. In the region where no boundary or only one or two grain boundaries are included, electric characteristics will vary greatly. For this reason, a great variance will occur in the characteristics between a plurality of devices, thereby posing remarkable obstacles in forming integrated circuits, etc.
Among the problems of the polycrystalline thin film of large grain size by solid phase crystallization as mentioned above, a method of suppressing variance of grain sizes has been proposed in, for example, Japanese Laid-open Patent Application No. 58-56406. That method is described by referring to FIGS. 1A and 1B. First, as shown in FIG. 1A, on the surface of an amorphous Si thin film 2 formed on the amorphous substrate 1, a thin film small strip 3 comprising another material is provided periodically, and the whole substrate is annealed in a conventional heating oven. Then, in the amorphous Si thin film 2, nucleation of a crystal nucleus 4 will occur preferentially from the site in contact with the peripheral side of the thin film small strip 3. Accordingly, when the crystal nucleus is further grown, the amorphous Si thin film 2 is crystallized over the whole region, whereby a polycrystalline thin film comprising a group of crystalline grains 5 with large grain sizes shown in FIG. 1B is obtained. According to Japanese Laid-open Patent Application No. 58-56406, it is stated that the variance of grain sizes can be reduced by this method to about 1/3 as compared with the prior art method previously shown.
However, yet considering the practical level, it cannot be said to be satisfactory in some cases. For example, when the thin film small strips 3 are arranged in lattice points with intervals of 10 .mu.m, the variance of grain sizes can be restricted within the range of about 3 to 8 .mu.m, but such level cannot be said to be satisfactory in most cases. Particularly, as to control of the positions of crystal boundaries, they are not controlled almost at all under the present situation. The reason is that preferential nucleation occurs at the peripheral sides of the thin film small strips 3 due to the localization effect of the elastic energy at the portions where amorphous Si thin film 2 contacts the peripheral side portions of the thin film small strips 3, whereby not only a plurality of nuclei are generated along the peripheral side, but also its number can be controlled with difficulty.
Concerning the method for controlling the nucleation positions in solid phase growth of amorphous Si thin film, other method is proposed, for example, in Japanese Laid-open Patent Application No. 63-253616. This is the method as shown in FIG. 2 in which a region 24 in which a substance 23 other than Si is locally ion-implanted into the amorphous Si thin film 22, to generate crystal nuclei preferentially there. As the substance 23 other than Si, N is proposed, and in that case, actually selectivity concerning nucleation between the region 24 ion-implanted and other regions 25 cannot be said to be necessarily satisfactory, and there has been no report about practical realization of this method to full satisfaction on practical level.